The performance of a computer system depends in particular on the performance of its processor (particularly its computational speed) and on the performance of the random access memory it uses to carry out the operations related to the execution of the instructions it is executing (in particular the memory read and write access times).
In communication systems for example, very high computational performance is expected while maintaining a limited cost and the shortest possible development time for the communication system.
The types of performance expected include the possibility of implementing real-time functionalities, such as for example the management of communication streams with increasingly large volumes of data to be processed. The implementation of these functionalities, however, must not adversely impact the implementation of other functionalities by the communication system. These real-time functionalities require significant computational resources because they involve the processing of a large amount of data within a minimum amount of time.
One solution consists of dedicating a processor to each type of functionality: one processor for real-time applications, and one processor for the other applications. This solution has the advantage of providing access to a large amount of computational power for running all the applications.
This solution significantly increases the cost of the communication system, however.
In addition, when it involves incorporating new real-time features into an existing hardware system that has only one processor, this solution is not a real possibility because it involves completely revising the system structure, which has a cost and involves a long development period.
Another solution consists of increasing the size of the primary memory cache (called the “L1 cache” by persons skilled in the art) in order to dedicate one part of the cache to real-time applications and the other part to the other applications.
It is thus possible to prepare a large volume of data and make them available to the processor very quickly. In fact, by having the data accessible in this cache, the number of instructions needed to obtain the memory from other memories is reduced.
However, this solution involves increasing the size of the components on the silicon of the chip in which the system is implanted. As a corollary, this solution implies a lower clock rate for the system.
In addition, there is a limit to how much the size of the L1 cache can be increased, beyond which the gain in computational speed becomes insignificant because the number of instructions for fetching specific data from the L1 cache becomes too high.